Generating Test Patterns for Bridge Faults in CMOS ICs
نویسندگان
چکیده
We describe a system for generating accurate tests for bridge faults (with or without feedback) in CMOS ICs. We present the Test Guarantee Theorem, which allows for accurate test generation for feedback bridge faults via topological analysis of the feedbackin uenced region of the faulted circuit (without the need for any post-test veri cation or explicit examination of inversion parity). We describe our test pattern generation system's treatment of feedback bridge faults in detail and report on the system's performance.
منابع مشابه
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
abstract Two approaches have been used to balance the cost of generating eeective tests for ICs and the need to increase the ICs' quality level. The rst approach favors using high-level fault models to reduce test generation costs at the expense of test quality, and the second approach favors the use of low-level, technology-speciic fault models to increase defect coverage but lead to unaccepta...
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References 1] M. Abramovici and P. R. Menon. A practical approach to fault simulation and test generation for bridging faults. IEEE Transactions on Computers , C-34:658{663, 1985. 2] J. M. Acken and S. D. Millman. Accurate mod-eling and simulation of bridging faults. In Pro-Campbell. Double-bridge test structure for the evaluation of type, size and density of spot defects. foreach feedback brid...
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